As before discussed, most of the high performance systems of this character tend to use bus-based architecture, where a system bus interconnects the CPU, the main memory and the I/O resources as shown in later-described FIG. 1, (the terms `main memory` and `system memory` as herein used, being so used interchangeably). This is relatively straight forward design and provides room for expansion; but it has serious limitations. Whenever the CPU or the peripherals need to access the main memory (generally implemented with DRAM), an arbitration takes place for access to the system bus. Thus the amount of concurrent activity in the system is limited by the overall capacity of the external bus.
As the speed of the CPU OR I/O Resource increases, the system bus bandwidth must correspondingly increase to realize the full potential of the system. Increasing the bus bandwidth, however, is much more difficult and very costly to the point of becoming technically impossible or prohibitively expensive. In addition, the number of I/O resources which can be on the bus is also limited by the bandwidth. It should be noted indeed that while theoretically the single bus allows a high order of expandability, the real operation due to contentions, drastically limits such expansion.
This problem is prevalent among all types of applications. While illustrative networking and graphics applications are presented hereafter as examples for better understanding of these problems, the invention is in no way limited to these exemplary areas only.